1. Field of the Invention
The present invention relates to cryptographic equipment and is particularly concerned with cryptographic equipment composed of an encoder at the transmitting side and a decoder at the receiving side each respectively provided with a synchronization device for bit-by-bit encoding at the transmitting side and bit-by-bit decoding at the receiving side of a bit stream having a high bit repetition frequency and that represents a binary signal.
2. Description of the Prior Art
Cryptographic equipment of the type generally set forth above are particularly realized in mobile radio systems having integrated circuits in complementary metal-oxide-semiconductor (CMOS) technology since minimum dimensions given extraordinarily low power consumption of the required circuits are thereby achieved. However, the operating speed of such integrated circuits constructed in accordance with CMOS technology cannot be selected arbitrarily high. When, for example, bit streams on the order of magnitude of Mbit and above are to be encoded, then the operating speeds required for this purpose exceed the maximally-possible working speed of integrated circuits that can be executed in accordance with CMOS technology.
In order to alleviate this situation, it has already been proposed to design the encoder at the transmitting side with n subcoders and to design the decoder at the receiving side with n subdecoders that correspond to the subcoders, in particular in such a fashion that a demultiplexer that respectively divides the bit stream to the subcoders and subdecoders into n bit streams is thereby allocated at the input side to the n subcoders and subdecoders and a multiplexer that, in turn, combines the coded or, respectively, decoded bit sub-streams into the coded, or respectively, decoded bit stream is thereby respectively assigned to the n subcoders and subdecoders at the output side. The synchronization device for the encoder at the transmitting side and for the decoder at the receiving side is thereby then respectively designed for an individual synchronization of the n subcoders or, respectively, subdecoders assigned thereto.
Given the utilization of such encoders at the transmitting side and decoders at the receiving side, care must be exercised in order to guarantee an error-free transmission of the bit stream encoded in this manner to see that a frame synchronization with respect to the bit substreams is also present in addition to a faultless, mutual synchronization between the subcoders of the transmitting side and subdecoders of the receiving side that are assigned to one another. In a previous Obermaier et al patent application, Ser. No. 386,802, filed Jul. 27, 1989, this additional frame synchronization is accomplished by additional, mutual synchronization between the demultiplexer and the multiplexer both at the encoder of the transmitting side and at the decoder of the receiving side, this causing an additional expense. The disclosure of the aforesaid Obermaier et al application is hereby incorporated hereinto.